3819 datasheet(9/218 Pages) RENESAS

9 / 218 page

3819 Group USER’S MANUAL

Table of contents

List of figures

CHAPTER 1. HARDWARE

Fig. 1 Structure of CPU mode register ................................................................................................. 8

Fig. 2 Memory map .................................................................................................................................. 9

Fig. 3 Memory map of special function register (SFR) .................................................................... 10

Fig. 4 Port block diagram (1) ............................................................................................................... 13

Fig. 5 Port block diagram (2) ............................................................................................................... 14

Fig. 6 Port block diagram (3) ............................................................................................................... 15

Fig. 7 Port block diagram (4) ............................................................................................................... 16

Fig. 8 Interrupt control ........................................................................................................................... 18

Fig. 9 Structure of interrupt related registers ..................................................................................... 18

Fig. 10 Timer block diagram ................................................................................................................. 20

Fig. 11 Structure of timer related registers ........................................................................................ 21

Fig. 12 Timing in timer 6 PWM mode ................................................................................................. 22

Fig. 13 Serial I/O block diagram .......................................................................................................... 24

Fig. 14 Structure of serial I/O control registers ................................................................................. 25

Fig. 15 Serial I/O timing in the serial I/O ordinary mode (for LSB first) ....................................... 26

Fig. 16 Structure of serial I/O automatic transfer control register .................................................. 26

Fig. 17 Bit allocation of serial I/O automatic transfer RAM ............................................................. 27

Fig. 18 Serial I/O automatic transfer interval timing ......................................................................... 27

Fig. 19 Serial I/O1 register transfer operation in full duplex mode ................................................ 28

Fig. 20 Timing chart during serial I/O automatic transfer

(internal clock selected, SRDY used) ..................................................................................... 29

Fig. 21 Timing chart during serial I/O automatic transfer

(internal clock selected, SCLK11 and SCLK12 used) .............................................................. 29

Fig. 22 Timing during serial I/O automatic transfer (external clock selected) .............................. 30

Fig. 23 Structure of A-D control register ............................................................................................ 31

Fig. 24 A-D converter block diagram .................................................................................................. 32

Fig. 25 D-A converter block diagram .................................................................................................. 32

Fig. 26 Equivalent connection circuit of D-A converter .................................................................... 32

Fig. 27 FLD control circuit block diagram .......................................................................................... 33

Fig. 28 Structure of FLDC mode register 1 ....................................................................................... 34

Fig. 29 Structure of FLDC mode register 2 ....................................................................................... 34

Fig. 30 Segment/digit setting example ................................................................................................ 35

Fig. 31 FLD automatic display RAM and bit allocation .................................................................... 37

Fig. 32 Example of using the FLD automatic display RAM (1) ....................................................... 38

Fig. 33 Example of using the FLD automatic display RAM (2) (continued) .................................. 39

Fig. 34 FLDC timing ............................................................................................................................... 40

Fig. 35 Block diagram of interrupt interval determination circuit ..................................................... 41

Fig. 36 Structure of interrupt interval determination control register .............................................. 42

Fig. 37 Interrupt interval determination operation example (at rising edge active) ...................... 42

Fig. 38 Interrupt interval determination operation example (at both-sided edge active) ............. 43

Fig. 39 External circuit example for zero cross detection ................................................................ 44

Fig. 40 Structure of zero cross detection control register................................................................ 44

Fig. 41 Block diagram of zero cross detection circuit ...................................................................... 44

Fig. 42 Noise filter circuit diagram ...................................................................................................... 45

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