7643 datasheet(216/424 Pages) RENESAS

216 / 424 page

Rev.2.00

Aug 28, 2006

page 95 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

2.5.7 Notes on DMAC

(1) Transfer time

•One-byte data transfer requires 2 cycles of

φ (read and write cycles).

•To perform DMAC transfer due to the different transfer requests on the same DMAC channel or

DMAC transfer between both DMAC channels, 1 cycle of

φ or more is needed before transfer is

started.

(2) Priority

•The DMAC places a higher priority on channel-0 transfer requests than on channel-1 transfer

requests.

If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC

completes the next transfer source and destination read/write operation first, and then stops the

channel-1 transfer operation.

The channel-1 transfer operation which has been suspended is automatically resumed from the

point where it was suspended so that channel-1 transfer can complete its one-burst transfer unit.

This will be performed even if another channel-0 transfer request occurs.

•The suspended transfer due to the interrupt can also be resumed during its interrupt process

routine by writing “1” to the DMAC channel x enable bit (DxCEN).

(3) Related registers

•A read/write must be performed to the source registers, transfer destination registers and transfer

count registers as follows:

Read from each higher byte first, then the lower byte

Write to each lower byte first, then the higher byte.

Note that if the lower byte is read out first, the values are the higher byte’s.

•Do not access the DMAC-related registers by using a DMAC transfer. The destination address

data and the source address data will collide in the DMAC internal bus.

•When setting the DMAC channel x enable bit (bit 7 of address 4116) to “1”, be sure simultaneously

to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address

4116) to “1”. If this is not performed, an incorrect data will be transferred at the same time when

the DMAC is enabled.

(4) DMAOUT pin

In the memory expansion mode and microprocessor mode, the DMAOUT pin (P33/DMAOUT) outputs

“H” during a DMA transfer.

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