7643 datasheet(58/424 Pages) RENESAS

58 / 424 page

Rev.2.00

Aug 28, 2006

page 41 of 103

REJ09B0133-0200

OVERVIEW

FUNCTIONAL DESCRIPTION

7643 Group

Fig. 33 Timing chart for burst transfer caused by hardware-related transfer request

ADL1

PC + 2

ADL1, 00

PC + 1

PC + 3

LDA $zz

STA $zz

(First cycle)

STA $zz

(Second cycle)

OUT

SYNCOUT

DMAOUT

(Port P33)

Address

Data

Transfer request

source (“L” active)

Transfer request source

sampling

Reset of transfer request

source sampling

DMA transfer

Data

DMA destina-

tion add. 1

DMA source

add. 1

DMA destina-

tion add. 2

DMA source

add. 2

DMA

data 1

DMA

data 1

DMA

data 2

DMA

data 2

ADL2

(2) Burst Transfer Mode

When the DMAC Channel x Transfer Mode Selection Bit (DxTMS)

is set to “1”, the respective DMAC channel operates in the burst

transfer mode.

In the burst transfer mode, the DMAC continually transfers the

number of bytes of data specified by the Transfer Count Register

for one transfer request. Other than this, the burst transfer mode

operation is the same as the cycle steal mode operation.

Priority

The DMAC places a higher priority on Channel-0 transfer requests

than on Channel-1 transfer requests.

If a Channel-0 transfer request occurs during a Channel-1 burst

transfer operation, the DMAC completes the next transfer source

and destination read/write operation first, and then starts the

Channel-0 transfer operation. As soon as the Channel-0 transfer is

completed, the DMAC resumes the Channel-1 transfer operation.

When an interrupt request occurs during any DMA operation, the

transfer operation is suspended and the interrupt process routine

is initiated. During the interrupt operation, the DMAC automatically

sets the corresponding DMAC Channel x (x = 0, 1) Suspend Flag

(DxSFI) to “1”. As soon as the CPU completes the interrupt opera-

tion, the DMAC clears the flag to “0” and resumes the original

operation from the point where it was suspended.

The suspended transfer due to the interrupt can also be resumed

during its interrupt process routine by writing “1” to the DMAC

Channel x (x = 0,1) Enable Bit (DxCEN).

The timing charts for a burst transfer caused by a hardware-re-

lated transfer request are shown in Figure 33.

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