7643 datasheet(72/424 Pages) RENESAS

72 / 424 page

Rev.2.00

Aug 28, 2006

page 55 of 103

REJ09B0133-0200

OVERVIEW

FUNCTIONAL DESCRIPTION

7643 Group

[USB endpoint x (x = 0 to 2) OUT Write Count Registers]

WRT_CNTR

This register contain the number of bytes in the endpoint x OUT

FIFO. This is read-only register. This register must be read after

the USB FCU has received a packet of data from the host.

When the OUT FIF0 is in double buffer mode, the CPU first reads

the received number of bytes of the former data packet. The next

CPU read can obtain that of the new data packet.

Fig. 48 Structure of USB endpoint x (x = 0 to 2) OUT write count registers

[USB Endpoint x (x = 0 to 2) FIFO Register] USBFIFOx

These registers are the USB IN (transmit) and OUT (receive) FIFO

data registers. Write data to the corresponding register, and read

data from the corresponding register.

When the maximum packet size is equal to or less than half the

FIFO size, these registers function in double buffer mode and can

hold two packets of data. When the IN_PKT_RDY bit is “0” and

the TX_NOT_EMPTY bit is “1”, these bits indicate that one packet

of data is stored in the IN FIFO. When the OUT FIFO is in double

buffer mode, the OUT_PKT_RDY flag remains as “1” after the first

packet of data is read out (it actually goes to “0” and returns to “1”

after one

φ cycle).

Endpoint x IN/OUT FIFO

USB endpoint x FIFO register

(addresses 006016, 006116, 006216)

USBFIFOx

Fig. 49 Structure of USB endpoint x (x = 0 to 2) FIFO register

The number of bytes in endpoint x OUT FIFO

USB endpoint x OUT write count register (address 005D16)

WRT_CNT

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