7643 datasheet(215/424 Pages) RENESAS

215 / 424 page

Rev.2.00

Aug 28, 2006

page 94 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.5 DMAC

Fig. 2.5.18 Control procedure

CCR (address 1F16)

FSM1 (address 6D16)

FSM2 (address 6E16)

FSD (address 6F16)

FSC (address 6C16)

USBC (address 1316)

USBINDEX (address 5816)

USBFIFOMR (address 5F16)

IN_MAXP (address 5B16)

IN_CSR (address 5916)

DMAIS (address 3F16)

DMA0SL (address4216)

DMA0SH (address 4316)

DMA0DL (address4416)

DMA0DH (address 4516)

DMA0CL (address4616)

DMA0CH (address 4716)

DMA0M1 (address 4016)

USBIE1 (address 5416)

IREQA (address 0216)

ICONA (address 0516)

DMA0M2 (address 4116)

CLI

0016

FF16

0016

4116

101100X02

000000102

000010002

8016

1XXXXXXX2

0XXXXX002

XX16

6216

0016

7F16

0016

100X0X0X2

0000XXXX2

0016

XXX1XXX02

110101102

RESET

•USB initialization

DMAC channel 0 interrupt

Data is available in external FIFO ?

RTI

Initialization

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

CLT (Note 1)

CLD (Note 2)

Push registers to stack

Note1: When using Index X mode flag (T)

2: When using Decimal mode flag (D)

•Push registers used in interrupt process routine

SEI

DMA0M2 (address 4116), bit 7

Pop registers

•Maximum packet size of 128 bytes

•External FIFO for source register

•USB FIFO1 for destination register

•USB endpoint 2 IN_PKT_RDY as hardware transfer request source

•USB endpoint 2 IN and OUT interrupts disabled

•DMAC channel 0 USB and master CPU bus interface disabled

•After confirming external FIFO state, generate the software transfer

trigger request

•If a data is deficient, stop the DMA transferring. After all data have

been available, resume the transfer.

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