7643 datasheet(369/424 Pages) RENESAS

369 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 46 of 98

Fig. 3.5.5 Structure of Interrupt request register C

Interrupt request register C

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register C

(IREQC : address 0416)

Name

Functions

At reset R W

Timer 3 interrupt request

bit

Serial I/O interrupt request

bit

Key input interrupt request

bit

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

✽

✽: “0” can be set by software, but “1” cannot be set.

Nothing is arranged for these bits.

When these bits are read out, the contents are undefined.

These bits are “0” at write.

Nothing is arranged for these bits.

When these bits are read out, the contents are undefined.

These bits are “0” at write.

Nothing is arranged for this bit.

Fix this bit to “0”.

Interrupt control register A

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt control register A

(ICONA : address 0516)

Name

Functions

At reset R W

USB function interrupt

enable bit

INT1 interrupt enable bit

DMAC0 interrupt enable

bit

UART receive buffer full

interrupt enable bit

INT0 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

DMAC1 interrupt enable

bit

UART transmit interrupt

enable bit

Nothing is arranged for this bit.

Fix this bit to “0”.

Fig. 3.5.6 Structure of Interrupt control register A

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