SH7014 datasheet(149/754 Pages) RENESAS

149 / 754 page

8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 115 of 716

REJ09B0398-0500

Bits 3 to 0

⎯CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2,

DSW1, DSW0): Specifies the number of waits for CS space access (0 to 15) during DMA single

address mode accesses. These bits are independent of the W bits of the WCR1.

Bit 3

DSW3

Bit 2

DSW2

Bit 1

DSW1

Bit 0

DSW0

Description

No wait (external wait input disabled)

1 wait (external wait input enabled)

⋅⋅⋅

15 wait (external wait input enabled)

(initial value)

8.2.5

DRAM Area Control Register (DCR)

DCR is a 16-bit read/write register that selects the number of waits, operation mode, number of

address multiplex shifts and the like for DRAM control.

After a power-on reset, write the initial values to the bits in DCR and do not change the values

afterward.

Do not perform any DRAM space accesses before DCR initial settings are completed.

DCR is initialized by power-on resets to H'0000, but is not initialized by software standbys.

Bit:

TPC

RCD

TRAS1

TRAS0

DWW1

DWW0

DWR1

DWR0

Initial value:

R/W:

R/W

Bit:

DIW

⎯

RASD

⎯

SZ0

AMX1

AMX0

Initial value:

R/W:

R/W

Bit 15

⎯RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after

RAS is negated before next assert.

Bit 15

TPC

Description

1.5 cycles

(initial value)

2.5 cycles

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