SH7014 datasheet(9/754 Pages) RENESAS

9 / 754 page

Rev.5.00 Sep. 27, 2007 Page ix of xxxiv

REJ09B0398-0500

Item

Page

Revision (See Manual for Details)

8.2.5 DRAM Area

Control Register (DCR)

115

Description amended

DCR is a 16-bit read/write register that selects the number of

waits, operation mode, number of address multiplex shifts and

the like for DRAM control.

After a power-on reset, write the initial values to the bits in DCR

and do not change the values afterward.

Do not perform any DRAM space accesses before DCR initial

settings are completed.

9.1.1 Features

147

Description amended

• Transfer requests: There are three DMAC transfer activation

requests, as indicated below.

⎯ External request: From two

DREQ pins. DREQ can be

detected either by falling edge or by low level. These

can be received by all channels.

9.2.3 DMA Transfer

Count Registers 0, 1

(DMATCR0, DMATCR1)

153

Description amended

… Specifying a H'000001 gives a transfer count of 1, while

H'000000 gives the maximum setting, 65,536 transfers. While

DMAC is in operation, the number of transfers to be performed

is indicated. The initial value after power-on resets or in

software standby mode is undefined.

Upper sixteen bits of this register are read as 0 and the write

value should always be 0.

9.3.5 Number of Bus

Cycle States and

DREQ

Pin Sample Timing

Cycle Steal Mode

Operations:

Figure 9.12 Cycle

Steal, Single Address

and Level Detection

(Normal Operation)

176

Note added

Note:

With cycle-steal and single address operation, sampling

timing is the same whether

DREQ detection is by level

or by edge.

Burst Mode, Single

Address, and Edge

Detection:

185

Description amended

…During this period, data is undefined, and DACK is not

output. Nor is the number of DMAC transfers counted. The

actual DMAC transfer begins after one dummy bus cycle

output. Thereafter, DMAC transfer continues until the data

transfer count set in the DMATCR has ended. ...

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