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HD64F2149YV bảng dữ liệu(PDF) 214 Page - Renesas Technology Corp

tên linh kiện HD64F2149YV
Giải thích chi tiết về linh kiện  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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Section 7 Data Transfer Controller
Rev. 3.00 Jan 18, 2006 page 186 of 1044
REJ09B0280-0300
7.3.6
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial address register state specified by the transfer counter and repeat area resumes and transfer
is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts
cannot be requested when DISEL = 0.
Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in
repeat mode.
Table 7.6
Register Information in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Transfer count
DTC transfer count register B
CRB
Not used
Transfer
Repeat area
SAR or
DAR
DAR or
SAR
Figure 7.7 Memory Mapping in Repeat Mode



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