HD64F2149YV datasheet(114/1075 Pages) RENESAS

114 / 1075 page

Section 3 MCU Operating Modes

Rev. 3.00 Jan 18, 2006 page 86 of 1044

REJ09B0280-0300

3.3

Operating Mode Descriptions

3.3.1

Mode 1

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.

Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries

bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus.

3.3.2

Mode 2

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.

After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use

external addresses.

When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset.

They can be set to output addresses by setting the corresponding bits in the data direction register

(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing

the ABW bit to 0 in the WSCR register makes port B a data bus.

3.3.3

Mode 3

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled.

After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use

external addresses.

When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They

can be set to output addresses by setting the corresponding bits in the data direction register

(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing

the ABW bit to 0 in the WSCR register makes port B a data bus.

In this operating mode, the available amount of on-chip ROM in products with 64 kbytes or more

of ROM is limited to 56 kbytes.

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