HD64F2149YV datasheet(112/1075 Pages) RENESAS

112 / 1075 page

Section 3 MCU Operating Modes

Rev. 3.00 Jan 18, 2006 page 84 of 1044

REJ09B0280-0300

3.2.4

Serial Timer Control Register (STCR)

IICS

R/W

IICX1

R/W

IICX0

R/W

IICE

R/W

FLSHE

R/W

ICKS0

R/W

—

R/W

ICKS1

R/W

Bit

Initial value

Read/Write

STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode

(when the on-chip IIC option is included), an on-chip flash memory control, and also selects the

TCNT input clock. For details of functions other than register access control, see the descriptions

of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the

corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 5—I

2C Control (IICS, IICX1, IICX0): These bits control the operation of the I2C bus

interface and others when the on-chip IIC option is included. For details, see section 16, I

2C Bus

Interface.

Bit 4—I

2C Master Enable (IICE): Controls CPU access to the I2C bus interface data registers

and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and

control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),

and the SCI control registers (SMR, BRR, and SCMR).

Bit 4

IICE

Description

Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and

H'(FF)FF8F, are used for SCI1 control register access

Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and

H'(FF)FFA7, are used for SCI2 control register access

Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and

H'(FF)FFDF, are used for SCI0 control register access

(Initial value)

Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and

H'(FF)FF8F, are used for IIC1 data register and control register access

Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and

H'(FF)FFA7, are used for PWMX data register and control register

access

Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and

H'(FF)FFDF, are used for IIC0 data register and control register access

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