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HD64F2149YV bảng dữ liệu(PDF) 346 Page - Renesas Technology Corp |
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HD64F2149YV bảng dữ liệu(HTML) 346 Page - Renesas Technology Corp |
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346 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 318 of 1044 REJ09B0280-0300 Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. Bit 2 OCIBE Description 0 Output compare interrupt request B (OCIB) is disabled (Initial value) 1 Output compare interrupt request B (OCIB) is enabled Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. Bit 1 OVIE Description 0 Timer overflow interrupt request (FOVI) is disabled (Initial value) 1 Timer overflow interrupt request (FOVI) is enabled Bit 0—Reserved: This bit cannot be modified and is always read as 1. 11.2.7 Timer Control/Status Register (TCSR) Bit Initial value Read/Write 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 4 ICFD 0 3 OCFA 0 0 CCLRA 0 R/W 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written in bits 7 to 1 to clear these flags. TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals. TCSR is initialized to H'00 by a reset and in hardware standby mode. Timing is described in section 11.3, Operation. Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software. |
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