M16CSLASH29 datasheet(244/499 Pages) RENESAS

244 / 499 page

14. Serial I/O

page 220

14.2.1 SI/Oi Operation Timing

Figure 14.37

shows the SI/Oi operation timing

Figure 14.37 SI/Oi Operation Timing

14.2.2 CLK Polarity Selection

The the SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 14.38

shows the polarity of the transfer clock.

Figure 14.38 Polarity of Transfer Clock

i= 3, 4

1.5 cycle (max)

SI/Oi internal clock

CLKi output

Signal written to the

SiTRR register

SOUTi output

SINi input

SiIC register

IR bit

(2)

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

(3)

NOTES:

1. This diagram applies to the case where the SiC register bits are set as follows:

SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data output at the falling edge and receive data input at the

rising edge of the transfer clock), SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)

2. When the SMi6 bit is set to 0 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer is completed.

3. If the SMi6 bit is set to 0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to

the SiTRR register.

(2) When the SMi4 bit in the SiC register is set to 1

(3)

SINi

SOUTi

CLKi

(1) When the SMi4 bit in the SiC register is set to 0

SINi

SOUTi

CLKi

(2)

i=3 and 4

NOTES:

1. This diagram applies to the case where the SiC register bits are set as follows:

SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)

2. When the SMi6 bit is set to 1 (internal clock), a high level is output from the CLKi pin if not transferring data.

3 When the SMi6 bit is set to 1 (internal clock), a low level is output from the CLKi pin if not transferring data.

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