M16CSLASH29 datasheet(99/499 Pages) RENESAS

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9. Interrupts

page 75

9.3 Interrupt Control

The following describes how to enable/disable the maskable interrupts, and how to set the priority in which

order they are accepted. What is explained here does not apply to nonmaskable interrupts.

Use I flag in the the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to

enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each

interrupt control register.

Figure 9.3

shows the interrupt control registers.

Also, the following interrupts share a vector and an interrupt control register.

________

•INT4 and SIO3

________

•INT5 and SIO4

•A/D converter and key input interrupt

•IC/OC base timer and SCL/SDA

•IC/OC interrupt 1 and I2C bus interface

An interrupt request is set by bits IFSR6 and IFSR7 in the IFSR register and bits IFSR27, IFSR26, and

IFSR21 in the IFSR2A register. Figure 9.4 shows registers IFSR register and IFSR2A.

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