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M16C/29 bảng dữ liệu(PDF) 70 Page - Renesas Technology Corp

tên linh kiện M16C/29
Giải thích chi tiết về linh kiện  RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
PDF  499 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M16C/29 bảng dữ liệu(HTML) 70 Page - Renesas Technology Corp

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The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to
interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-
eral bus. Figure 6.3 shows the block diagram of the internal bus.
CPU
ROM
BIU
I/O
CPU address bus
Memory data bus
DMAC
Memory address bus
Timer
WDT
Serial I/O
ADC
CAN
CRC
Peripheral function
CPU clock
RAM
CPU data bus
.
.
Clock
generation
circuit
Figure 6.3 Bus Block Diagram
Table 6.1 Accessible Area and Bus Cycle
The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.
Accessible Area
Bus Cycle
SFR
PM20 bit = 0 (2 waits)
3 CPU clock cycles
PM20 bit = 1 (1 wait)
2 CPU clock cycles
ROM/RAM
PM17 bit = 0 (no wait)
1 CPU clock cycle
PM17 bit = 1 (1 wait)
2 CPU clock cycles



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