M16CSLASH29 datasheet(117/499 Pages) RENESAS

117 / 499 page

11. DMAC

page 93

Figure 11.2 DM0SL Register

DMA0 Request Cause Select Register

Symbol

Address

After Reset

DM0SL

03B816

0016

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

DSR

Bit Name

DMS

(b5-b4)

Refer to note (1)

A DMA request is generated by

setting this bit to 1 when the DMS bit

is 0 (basic cause) and bits DSEL3 to

DSEL0 are 00012 (software trigger).

The value of this bit when read is 0

Software DMA request

bit

Nothing is assigned. When write, set to 0.

When read, their content are 0

DMA request cause

expansion select bit

0: Basic cause of request

1: Extended cause of request

NOTE:

1. The causes of DMA0 requests can be selected by a combination of DMS bit and bits DSEL3 to DSEL0 in the

manner described below.

DSEL3 to DSEL0 DMS=0(basic cause of request)

DMS=1(extended cause of request)

0 0 0 02

Falling edge of INT0 pin

IC/OC base timer

0 0 0 12

Software trigger

–

0 0 1 02

Timer A0

IC/OC channel 0

0 0 1 12

Timer A1

IC/OC channel 1

0 1 0 02

Timer A2

–

0 1 0 12

Timer A3

–

0 1 1 02

Timer A4

Two edges of INT0 pin

0 1 1 12

Timer B0

–

1 0 0 02

Timer B1

–

1 0 0 12

Timer B2

–

1 0 1 02

UART0 transmit

IC/OC channel 2

1 0 1 12

UART0 receive

IC/OC channel 3

1 1 0 02

UART2 transmit

IC/OC channel 4

1 1 0 12

UART2 receive

IC/OC channel 5

1 1 1 02

A/D conversion

IC/OC channel 6

1 1 1 12

UART1 transmit

IC/OC channel 7

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