M16CSLASH29 datasheet(120/499 Pages) RENESAS

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11. DMAC

page 96

11.1 Transfer Cycles

The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)

bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of

transfer. Furthermore, the bus cycle itself is extended by a software wait.

11.1.1 Effect of Source and Destination Addresses

If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source

read cycle consists of one more bus cycle than when the source address of transfer begins with an even

address.

Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address,

the destination write cycle consists of one more bus cycle than when the destination address of transfer

begins with an even address.

11.1.2 Effect of Software Wait

For memory or SFR accesses in which one or more software wait states are inserted, the number of bus

cycles required for that access increases by an amount equal to software wait states.

Figure 11.5

shows the example of the cycles for a source read. For convenience, the destination write

cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the

destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle

changing accordingly. When calculating transfer cycles, take into consideration each condition for the

source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit

units and when both the source address and destination address are an odd address ((2) in Figure 11.5),

two source read bus cycles and two destination write bus cycles are required.

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