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ST20-GP1 bảng dữ liệu(PDF) 106 Page - STMicroelectronics

tên linh kiện ST20-GP1
Giải thích chi tiết về linh kiện  GPS PROCESSOR
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ST20-GP1 bảng dữ liệu(HTML) 106 Page - STMicroelectronics

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®
19.4 ClockIn timings
Notes
1
Measured between corresponding points on consecutive falling edges.
2
Variation of individual falling edges from their nominal times.
3
Clock transitions must be monotonic within the range VIH to VIL (see Electrical Specifica-
tions).
Table 19.4 ClockIn timings
Figure 19.5 ClockIn timings
19.4.1 ClockIn frequency
Nominal ClockIn frequency is 16.36800 Mhz
±50 ppm tolerance. This tolerance relates to the GPS
system requirements and not for the device to function.
Symbol
Parameter
Min
Nom
Max
Units
Notes
tDCLDCH
ClockIn pulse width low for PLL operation
18
42.5
ns
tDCHDCL
ClockIn pulse width high for PLL operation
18
42.5
ns
tDCr
ClockIn rise time for PLL operation
20
ns
3
tDCf
ClockIn fall time for PLL operation
20
ns
3
tGDVCH
GPSIF valid before clock rising edge
20
ns
tCHGDX
GPSIF valid after clock rising edge
0
ns
90%
10%
tDCr
2.0V
0.8V
1.5V
tDCLDCH
tDCHDCL
tDCf
90%
10%
tGDVCH tCHGDX
GPSIF



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