ST20-GP1 datasheet(54/116 Pages) STMICROELECTRONICS

54 / 116 page

ST20-GP1

54/116

Figure 9.3 shows the generic EMI activity during a write access. notMemOE is inactive during a

write access, and the function of notMemWB1 is dictated by the bus width of the bank in the same

way as for a read access. MemData8-15 is held in high impedance during a write access if the bus

width is 8-bit, otherwise it follows the timing conﬁgured for MemData0-7.

Figure 9.3 Conﬁguration parameters for a write access

The following caveats relate to strobe edge programming:

•

If any of the strobe edges are programmed to occur outside the period deﬁned by Access-

Duration, the activity for that strobe is undeﬁned.

•

If a strobe’s rising and falling edges are programmed to occur on the same system clock

edge, they will nullify each other and the strobe will stay in the same state. This rule also

applies for consecutive accesses.

Transactions normally consist of several accesses which run consecutively without any ‘dead

cycles’. The number of accesses in a transaction is dependent on the bus width and the nature of

the memory bus request. Table 9.3 lists the transaction composition and the behavior of

MemAddr1 and notMemWB0-1 for each access.

MemAddr1-19

notMemWB1*

notMemCE

notMemWB0

MemData0-7

MemData8-15†

Access duration

CEe1 time

CEe2 time

WBe1 time

* Only when bus width is 8-bit. When bus width is 16-bit, notMemWB1 follows the timing

WBe2 time

speciﬁed for notMemWB0.

† Held in high impedance when bus width is 8-bit.

Data drive delay

(MemAddr0)

ST20-GP1 bảng dữ liệu(PDF) 54 Page - STMicroelectronics