ST20-GP1 datasheet(64/116 Pages) STMICROELECTRONICS

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ST20-GP1

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LPAlarmLS and LPAlarmMS

The LPAlarmLS and LPAlarmMS registers are the least signiﬁcant word and most signiﬁcant word

of the LPAlarm register. This is used to program the low power alarm.

Table 10.5 LPAlarmLS register format

Table 10.6 LPAlarmMS register format

LPAlarmStart

A write to the LPAlarmStart register starts the low power alarm counter. The counter is stopped

and the LPStart register reset if either counter word (LPTimerLS and LPTimerMS) is written.

Table 10.7 LPAlarmStart register format

LPSysPll

The LPSysPll register controls the System Clock PLL operation when low power mode is entered.

This allows a compromise between wake-up time and power consumption during stand-by.

Table 10.8 LPSysPll register format

LPAlarmLS

LPC base address + #410

Read/Write

Bit

Bit ﬁeld

Function

31:0

LPAlarmLS

Least signiﬁcant word of the low power alarm.

LPAlarmMS

LPC base address + #414

Read/Write

Bit

Bit ﬁeld

Function

7:0

LPAlarmMS

Most signiﬁcant word of the low power alarm.

LPAlarmStart

LPC base address + #418

Write

Bit

Bit ﬁeld

Function

LPAlarmStart

A write to this bit starts the low power alarm counter.

LPSysPll

LPC base address + #420

Read/Write

Bit

Bit ﬁeld

Function

1:0

LPSysPll

Determines the system clock PLL when low power mode is entered, as follows:

LPSysPll1:0

System clock

PLL off

PLL reference on and power on

PLL on

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