NRF52810-QFAA-R datasheet(269/483 Pages) NORDIC

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Peripherals

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

RW UPDOWN

Selects up or up and down as wave counter mode

Up counter - edge aligned PWM duty-cycle

UpAndDown

Up and down counter - center aligned PWM duty cycle

6.12.5.7 COUNTERTOP

Address offset: 0x508

Value up to which the pulse generator counter counts

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A A A A A A A A A A A A A A

Reset 0x000003FF

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

RW Field

Value Id

Value

Description

RW COUNTERTOP

[3..32767]

Value up to which the pulse generator counter counts. This

only values from RAM will be used.

6.12.5.8 PRESCALER

Address offset: 0x50C

Configuration for PWM_CLK

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

RW PRESCALER

Pre-scaler of PWM_CLK

DIV_1

Divide by 1 (16MHz)

DIV_2

Divide by 2 ( 8MHz)

DIV_4

Divide by 4 ( 4MHz)

DIV_8

Divide by 8 ( 2MHz)

DIV_16

Divide by 16 ( 1MHz)

DIV_32

Divide by 32 ( 500kHz)

DIV_64

Divide by 64 ( 250kHz)

DIV_128

Divide by 128 ( 125kHz)

6.12.5.9 DECODER

Address offset: 0x510

Configuration of the decoder

4430_161 v1.0

269

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