NRF52810-QFAA-R datasheet(94/483 Pages) NORDIC

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6 Peripherals

6.1 Peripheral interface

Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral

events are indicated to the CPU by event registers and interrupts if they are configured for a given event.

Peripheral

core

TASK

Task signal from PPI

write

task

event

EVENT m

IRQ signal to NVIC

INTEN

Peripheral

SHORTS

Event signal to PPI

Figure 21: Tasks, events, shortcuts, and interrupts

6.1.1 Peripheral ID

Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit

registers.

See Instantiation on page 17 for more information about which peripherals are available and where they

are located in the address map.

There is a direct relationship between the peripheral ID and base address. For example, a peripheral with

base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1,

and a peripheral with base address 0x4001F000 is assigned ID=31.

Peripherals may share the same ID, which may impose one or more of the following limitations:

• Some peripherals share some registers or other common resources.

• Operation is mutually exclusive. Only one of the peripherals can be used at a time.

• Switching from one peripheral to another must follow a specific pattern (disable the first, then enable

the second peripheral).

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