R5F121BCAFP datasheet(60/85 Pages) RENESAS

60 / 85 page

RL78/G16

3. ELECTRICAL SPECIFICATIONS (TA

= −40 to +105°C, TA = −40 to +125°C)

R01DS0431EJ0130

Rev.1.30

Page 60 of 85

May 19, 2025

3.4

AC Characteristics

[TA =

−40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V]

Item

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Instruction cycle (minimum

instruction execution time)

TCY

When high-speed on-chip

oscillator clock (fIH) is

selected

2.4 V

≤ VDD ≤ 5.5 V

0.0625

1.0

µs

When high-speed system

clock (fMX) is selected

2.4 V

≤ VDD ≤ 5.5 V

0.0833

1.0

µs

Subsystem clock (fSUB)

operation

2.4 V

≤ VDD ≤ 5.5 V

28.5

30.5

31.3

µs

In the self-programming

mode

2.4 V

≤ VDD ≤ 5.5 V

0.0625

1.0

µs

External system clock

frequency

fEX

2.4 V

≤ VDD ≤ 5.5 V

1.0

MHz

External system clock input

high-level width, low-level

width

tEXH, tEXL

2.4 V

≤ VDD ≤ 5.5 V

TI00 to TI07 input high-level

width, low-level width

tTIH, tTIL

Noise filter is not used

1/fMCK + 10

TO00 to TO07 output

frequency

fTO

4.0 V

≤ VDD ≤ 5.5 V

MHz

2.7 V

≤ VDD < 4.0 V

MHz

2.4 V

≤ VDD < 2.7 V

MHz

PCLBUZ0 output frequency

fPCL

4.0 V

≤ VDD ≤ 5.5 V

MHz

2.7 V

≤ VDD < 4.0 V

MHz

2.4 V

≤ VDD < 2.7 V

MHz

RESET

¯¯¯¯¯¯ low-level width

tRSL

µs

Remark

fMCK: Timer array unit operating clock frequency

(Operation clock to be set by timer clock select register 0 (TPS0) and the CKS0n1 bit of timer mode register

0n (TMR0n). n: Channel number (n = 0 to 7).)

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