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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS2020 bảng dữ liệu(PDF) 60 Page - Texas Instruments |
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TAS2020 bảng dữ liệu(HTML) 60 Page - Texas Instruments |
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60 / 79 page  7.5 PAGE 5 Registers Table 7-78 lists the memory-mapped registers for the PAGE 5 registers. All register offset addresses not listed in Table 7-78 should be considered as reserved locations and the register contents should not be modified. Table 7-78. PAGE 5 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.5.1 64h THERMAL_WARN_MIN_TEMP Thermal Flag Section 7.5.2 68h THERMAL_WARN_TEMP_STEP Thermal Flag Section 7.5.3 7.5.1 PAGE Register (Address = 0h) [Reset = 00h] Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-79. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255 7.5.2 THERMAL_WARN_MIN_TEMP Register (Address = 64h) [Reset = 348000h] Return to the Summary Table. Set the minimum threshold for Thermal Flag Table 7-80. THERMAL_WARN_MIN_TEMP Register Field Descriptions Bit Field Type Reset Description 23-0 THERMAL_WARN_MIN_T EMP[23:0] R/W 348000h Addresses 0x64 to 0x66 are combined. Can be configured using the PPC3 Software. 7.5.3 THERMAL_WARN_TEMP_STEP Register (Address = 68h) [Reset = 050000h] Return to the Summary Table. Set the delta threshold for Thermal Flag Table 7-81. THERMAL_WARN_TEMP_STEP Register Field Descriptions Bit Field Type Reset Description 23-0 THERMAL_WARN_TEMP _STEP[23:0] R/W 50000h Addresses 0x68 to 0x6A are combined. Can be configured using the PPC3 Software. TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 www.ti.com 60 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TAS2020 |
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