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TAS2020 bảng dữ liệu(PDF) 47 Page - Texas Instruments |
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TAS2020 bảng dữ liệu(HTML) 47 Page - Texas Instruments |
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47 / 79 page  This register configures Masks for Interrupt flags. Table 7-32. INT_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7 INT_MASK3[7] R/W 0h Mask for Interrupt due to over temperature detected 0h = Don't Mask 1h = Mask 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 RESERVED R 0h Reserved 3 INT_MASK3[3] R/W 0h Mask for Interrupt due to Class-D Over current protection 0h = Don't Mask 1h = Mask 2 INT_MASK3[2] R/W 0h Mask for Interrupt due to pvdd_ov_flag 0h = Don't Mask 1h = Mask 1 RESERVED R 0h Reserved 0 RESERVED R 0h Reserved 7.1.32 INT_MASK_4 Register (Address = 5Fh) [Reset = 0Ah] Return to the Summary Table. This register configures Masks for Interrupt flags. Table 7-33. INT_MASK_4 Register Field Descriptions Bit Field Type Reset Description 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 RESERVED R 0h Reserved 3 RESERVED R 0h Reserved 2 INT_MASK4[2] R/W 0h Mask for Interrupt due to clock halt flag. This interrupt also flags errors due to Pre-power-up clock error while using Wake-up-on-ASI feature 0h = Don't Mask 1h = Mask 1 RESERVED R 0h Reserved 0 RESERVED R 0h Reserved 7.1.33 INT_LATCH_0 Register (Address = 60h) [Reset = 00h] Return to the Summary Table. This register provides the status of latched interrupts. Table 7-34. INT_LATCH_0 Register Field Descriptions Bit Field Type Reset Description 7 INT_LTCH0[7] R 0h Interrupt due to BOP Inf Hold flag 0h = No interrupt 1h = Interrupt 6 INT_LTCH0[6] R 0h Interrupt due to limiter attentuation flag 0h = No interrupt 1h = Interrupt 5 INT_LTCH0[5] R 0h Interrupt due to supply less than inf pt flag 0h = No interrupt 1h = Interrupt www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TAS2020 |
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