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TAS2020 bảng dữ liệu(PDF) 44 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TAS2020 3.2W Mono Digital Input Class-D Speaker Amp with 5.5V PVDD Support
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Table 7-23. INTERRUPT_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
Shared_boost_secondary
_en
R/W
0h
Secondary device control in shared boost mode
0h = Disabled
1h = Enabled
5-2
RESERVED
R
0h
Reserved
1
INT_CLR_LTCH
R/W
0h
Clear INT_LTCH registers.
0h = Don't clear
1h = Clear
0
RESERVED
R
0h
Reserved
7.1.23 SAR_MONITOR_03 Register (Address = 28h) [Reset = 00h]
Return to the Summary Table.
This register provides sensed SAR ADC voltage.
Table 7-24. SAR_MONITOR_03 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PVDD_CNV_MSB[7:0]
R
0h
Returns the SAR ADC PVDD monitored voltage MSBs.
7.1.24 SAR_MONITOR_04 Register (Address = 29h) [Reset = 00h]
Return to the Summary Table.
This register provides sensed SAR ADC voltage.
Table 7-25. SAR_MONITOR_04 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
PVDD_CNV_LSB[3:0]
R
0h
Returns the SAR ADC PVDD monitored voltage LSBs.
3-0
RESERVED
R
0h
Reserved
7.1.25 SAR_MONITOR_06 Register (Address = 2Ah) [Reset = 00h]
Return to the Summary Table.
This register provides sensed temperature.
Table 7-26. SAR_MONITOR_06 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TMP_CNV[7:0]
R
0h
Returns the SAR ADC Temperature monitored data.
7.1.26 CLASSD_CFG_01 Register (Address = 31h) [Reset = 04h]
Return to the Summary Table.
This register configures the class-D amplifier.
Table 7-27. CLASSD_CFG_01 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
Reserved
5-4
CLASSD_OUTPUT_EDG
ERATE_CTRL[1:0]
R/W
0h
Edgerate programmability control.
0h = Class-D output edge rate of approximately 0.5V/ns
1h = Class-D output edge rate of approximately 1V/ns
2h = Reserved
3h = Class-D output edge rate of approximately 2V/ns
TAS2020
SLASFD4A – AUGUST 2024 – REVISED JULY 2026
www.ti.com
44
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