TAS2020 datasheet(16/79 Pages) TI2

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Table 6-4. SEL2 HW Mode configuration (continued)

SEL2 Connection

Configuration

330Ω to IOVDD

I2S R or TDM1

Direct Short to IOVDD

I2S (L+R)/2 or TDM2

1.2kΩ to GND

Left-Justified L or TDM3

1.2kΩ to IOVDD

Left-Justified R or TDM4

5kΩ to GND

Left-Justified (L+R)/2 or TDM5

5kΩ to IOVDD

I2S L or TDM6

24kΩ to GND

I2S R or TDM7

24kΩ to IOVDD

Reserved

Table 6-5. SEL3 HW Mode configuration

SEL3 Connection

Configuration

Direct Short to GND

Data valid on rising edge

Direct Short to IOVDD

Data valid on falling edge

Table 6-6. SEL4 HW Mode configuration

SEL4 Connection

Configuration

Direct Short to GND

Y-bridge threshold of 80mW

Direct Short to IOVDD

Y-bridge threshold of 40mW

24kΩ to IOVDD

Y-bridge threshold of 1mW

6.3.1.3 Software Power Modes Control and Software Reset

When SEL1 pin is shorted to GND, TAS2020 is configured in I2C Mode and can be configured by modifying

configuration registers over I2C interface.

TAS2020 power state can be controlled using the register MODE[1:0]. Change in any of the MODE settings will

not cause the device to lose any of the existing device configuration register settings.

Table 6-7. Software Mode Control

MODE[1:0]

Configuration

Device in active mode of

operation

Reserved

10 (default)

Device in software shutdown

mode

Device in Clock based Active and

shutdown mode

Active state: When MODE[1:0] is configured as '00', the device enters an active mode of operation with proper

power-up sequencing to minimize the click and pop.

Software shutdown state: When MODE[1:0] is configured as '10', the device enters software shutdown mode.

This mode powers down all analog blocks required to playback audio but does not cause the device to lose

before shutting down. When de-asserted, the Class-D will begin switching and volume ramp back to the

programmed digital volume setting.

Clock based Active and shutdown state: When MODE[1:0] is configured as '11' the device toggles between

Active and Shutdown state based on valid ASI clock signals applied on the ASI input pins, BCLK and FSYNC.

When clocks are applied, the device will automatically detect the clock signals and follow proper power-up

sequencing to avoid any power-up click and pop. When the audio channels are powered up and the ASI

clock is removed, the device will automatically start power-down sequencing and avoid any click and pop. It is

TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

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