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TAS2020 bảng dữ liệu(PDF) 53 Page - Texas Instruments |
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TAS2020 bảng dữ liệu(HTML) 53 Page - Texas Instruments |
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53 / 79 page  7.3 PAGE 2 Registers Table 7-47 lists the memory-mapped registers for the PAGE 2 registers. All register offset addresses not listed in Table 7-47 should be considered as reserved locations and the register contents should not be modified. Table 7-47. PAGE 2 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.3.1 Ch DVC_LEVEL Digital Volume Control Level Section 7.3.2 10h DVC_SLEW_RATE Digital Volume Control Slew Rate Section 7.3.3 18h AUDIO_HPF_N0 Set Audio DC Blocker filter coefficients Section 7.3.4 1Ch AUDIO_HPF_N1 Set Audio DC Blocker filter coefficients Section 7.3.5 20h AUDIO_HPF_D1 Set Audio DC Blocker filter coefficients Section 7.3.6 54h TONE_GEN_CNTRL_01 Tone generator Frequency Control register Section 7.3.7 58h TONE_GEN_CNTRL_02 Tone generator Frequency Control register Section 7.3.8 5Ch TONE_GEN_CNTRL_03 Tone generator Frequency Control register Section 7.3.9 60h TONE_GEN_CNTRL_04 Tone generator Frequency Control register Section 7.3.10 64h TONE_GEN_CNTRL_05 Tone generator Frequency Control register Section 7.3.11 68h TONE_GEN_CNTRL_06 Tone generator amplitude control register Section 7.3.12 7.3.1 PAGE Register (Address = 0h) [Reset = 00h] Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-48. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255 7.3.2 DVC_LEVEL Register (Address = Ch) [Reset = 400000h] Return to the Summary Table. Digital Volume Control Level Table 7-49. DVC_LEVEL Register Field Descriptions Bit Field Type Reset Description 23-0 DVC_LEVEL[23:0] R/W 400000h Addresses 0xC to 0xE are combined. Can be configured using the PPC3 Software. 7.3.3 DVC_SLEW_RATE Register (Address = 10h) [Reset = 034A51h] Return to the Summary Table. Digital Volume Control Slew Rate Table 7-50. DVC_SLEW_RATE Register Field Descriptions Bit Field Type Reset Description 23-0 DVC_SLEW_RATE[23:0] R/W 34A51h Addresses 0x10 to 0x12 are combined. Can be configured using the PPC3 Software. www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TAS2020 |
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