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TAS2020 bảng dữ liệu(PDF) 35 Page - Texas Instruments |
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TAS2020 bảng dữ liệu(HTML) 35 Page - Texas Instruments |
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35 / 79 page  7.1 PAGE 0 Registers Table 7-1 lists the memory-mapped registers for the PAGE 0 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified. Table 7-1. PAGE 0 Registers Address Acronym Description Section 0h Page Device Page Section 7.1.1 1h SW_RESET Software Reset Section 7.1.2 2h PWR_CTL Power Control Section 7.1.3 3h DEVICE_CFG_01 Device configuration registers Section 7.1.4 4h DEVICE_CFG_02 Device configuration registers Section 7.1.5 5h DEVICE_CFG_03 Device configuration registers Section 7.1.6 6h DEVICE_CFG_04 Device configuration registers Section 7.1.7 7h DEVICE_CFG_05 Device configuration registers Section 7.1.8 8h TDM_CFG1 TDM Configuration registers Section 7.1.9 9h TDM_CFG2 TDM Configuration registers Section 7.1.10 Ah TDM_CFG3 TDM Configuration registers Section 7.1.11 Ch TDM_CFG5 TDM Configuration registers Section 7.1.12 10h TDM_CFG9 TDM Configuration registers Section 7.1.13 11h TDM_CFG10 TDM Configuration registers Section 7.1.14 12h TDM_CFG11 TDM Configuration registers Section 7.1.15 13h TDM_CFG12 TDM Configuration registers Section 7.1.16 14h TDM_DET TDM Clock detection monitor Section 7.1.17 18h BOP_CFG_0 Brown out protection configuration Section 7.1.18 1Ch IO_CFG_02 IO Configuration Section 7.1.19 1Dh IO_CFG_03 IO Configuration Section 7.1.20 1Eh NG_CFG0 Noise Gate Controls Section 7.1.21 25h INTERRUPT_CFG1 IRQZ clear Section 7.1.22 28h SAR_MONITOR_03 PVDD Monitor MSB Section 7.1.23 29h SAR_MONITOR_04 PVDD Monitor LSB Section 7.1.24 2Ah SAR_MONITOR_06 Temperature monitor Section 7.1.25 31h CLASSD_CFG_01 ClassD amp configurations Section 7.1.26 3Ch THERM_CFG Thermal warning configuration Section 7.1.27 5Bh INT_MASK_0 Interrupt Masks Section 7.1.28 5Ch INT_MASK_1 Interrupt Masks Section 7.1.29 5Dh INT_MASK_2 Interrupt Masks Section 7.1.30 5Eh INT_MASK_3 Interrupt Masks Section 7.1.31 5Fh INT_MASK_4 Interrupt Masks Section 7.1.32 60h INT_LATCH_0 Latched interrupt readback Section 7.1.33 61h INT_LATCH_1 Latched interrupt readback Section 7.1.34 62h INT_LATCH_2 Latched interrupt readback Section 7.1.35 63h INT_LATCH_3 Latched interrupt readback Section 7.1.36 64h INT_LATCH_4 Latched interrupt readback Section 7.1.37 65h NG_IDLE_STATUS Latched interrupt readback Section 7.1.38 78h REV_ID Revision ID Section 7.1.39 7Fh BOOK Device Book Section 7.1.40 www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TAS2020 |
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