JS48F4400P0P3C0 datasheet(29/139 Pages) NUMONYX

29 / 139 page

April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

Notes:

F4-CE# and A27 share the same package ball at location E6. Only one signal function is available, depending on the

stacked device combination.

Only available on stacked device combinations with NAND, SRAM, and/or LPSDRAM die; otherwise, treated as RFU.

D-DM[1:0] and S-UB#/S-LB# share the same package balls at locations H8 and H9, respectively. Only one signal function

for each ball location is available, depending on the stacked device combination.

S-CS1# and N-RE# share the same package ball at location F6. Only one signal function is available, depending on the

stacked device combination.

S-CS2 and N-WE# share the same package ball at location H2. Only one signal function is available, depending on the

stacked device combination.

In stack packages with only one NOR flash die, this signal can be left floating.

4.3

Ballouts, x16C

4.3.1

x16C (107-Ball) Ballout, Non-Mux

D-DM[1:0]

Input

LPSDRAM DATA MASK: LPSDRAM-specific signal; high-true input.

When high, D-DM[1:0] controls masking of input data during writes and output data during

reads.

• D-DM1 corresponds to the data on DQ[15:8].

• D-DM0 corresponds to the data on DQ[7:0].

2, 3

D-UDQS

D-LDQS

Input /

Output

LPSDRAM UPPER/LOWER DATA STROBE: DDR LPSDRAM-specific input/output signals.

D-UDQS and D-LDQS provide as output the read-data strobes, and as input the write-data

strobes.

• D-UDQS corresponds to the data on DQ[15:8].

• D-LDQS corresponds to the data on DQ[7:0].

S-CS1#

S-CS2

Input

SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.

When both are asserted, S-CS1# and S-CS2 select the SRAM die. When either is deasserted, the

SRAM die is deselected and its power is reduced to standby levels.

2, 4, 5

S-UB#

S-LB#

Input

SRAM UPPER/LOWER BYTE ENABLES: SRAM-specific signals; low-true inputs.

When low, S-UB# enables DQ[15:8] and S-LB# enables DQ[7:0] during SRAM Read and Write

cycles. When high, S-UB# masks DQ[15:8] and S-LB# masks DQ[7:0].

2, 3

Power Signals

F-VPP

Power

FLASH PROGRAM/ERASE VOLTAGE: Flash specific.

F-VPP supplies program or erase power to the flash die.

F1-VCC

Power

FLASH CORE POWER SUPPLY: Flash specific.

F1-VCC supplies the core power to the NOR flash die.

F2-VCC

Power

FLASH CORE POWER SUPPLY: Flash specific.

F2-VCC supplies the core power to either 1) the NOR flash die in stack packages with multiple

NOR flash dies, or 2) NAND flash die in stack packages with NOR-NAND flash dies.

VCCQ

Power

I/O POWER SUPPLY: Global device I/O power.

VCCQ supplies the device input/output driver voltage.

D-VCC

Power

LPSDRAM CORE POWER SUPPLY: LPSDRAM specific.

D-VCC supplies the core power to the LPSDRAM die.

S-VCC

Power

SRAM POWER SUPPLY: SRAM specific.

S-VCC supplies the core power to the SRAM die.

VSS

Groun

DEVICE GROUND: Global ground reference for all signals and power supplies.

Connect all VSS balls to system ground. Do not float any VSS connections.

—

DO NOT USE:

Ball should not be connected to any power supplies, signals, or other balls. Ball can be left

floating.

RFU

—

RESERVED FOR FUTURE USE:

Reserved by Numonyx for future device functionality/enhancement. Ball must be left floating.

Table 7:

Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 4 of 4)

Symbol

Type

Signal Descriptions

Notes

JS48F4400P0P3C0 bảng dữ liệu(PDF) 29 Page - Numonyx B.V

JS48F4400P0P3C0 bảng dữ liệu(HTML) 29 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL