| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
JS48F4400P0P3C0 bảng dữ liệu(PDF) 73 Page - Numonyx B.V |
|
|
|||||||||||||||||||||||||||||
JS48F4400P0P3C0 bảng dữ liệu(HTML) 73 Page - Numonyx B.V |
|
73 / 139 page ![]() April 2008 Datasheet 309823-10 73 Numonyx™ StrataFlash® Cellular Memory (M18) Notes: 1. X = don’t care (high or low). 2. Active: WAIT asserted = invalid data; WAIT deasserted = valid data. 8.2 Bus Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. All device write operations are asynchronous, with CLK being ignored, but CLK can be kept active/toggling. During a write operation in non-muxed devices, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. During a write operation in muxed devices, address is latched during the rising edge of ADV# OR CE# whichever occurs first and Data is latched during the rising edge of WE# OR CE# whichever occurs first. 8.3 Reset The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. The device shuts down any operation in progress, a process which takes a minimum amount of time to complete. To return from reset mode, RST# must be deasserted. Normal operation is restored after a wake-up interval. 8.4 Deep Power-Down The device enters DPD mode when the following two conditions are met: ECR15 is set(1) and DPD is asserted. The two conditions can be satisfied in any order. ECR14 bit determines the DPD asserted logic level. While in this mode, RST# and CE# must be deasserted. The device exits DPD mode when DPD is deasserted. There is an exit latency before the device returns to standby mode and any operations are allowed. See the datasheet for the timing specifications. The device should not be placed in DPD mode when a program/erase operation is ongoing or suspended. If the device enters DPD mode in the middle of a program, erase or suspend, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid. Table 28: WAIT Behavior Summary Device Operation CE# OE# WE# WAIT Notes Device not selected Standby High X X High-Z 1 Non-Mux Device Output Disable Low High High High-Z Sync Read Low High Active 2 Async Read Low High Deasserted Write High Low High-Z AD-Mux Device Output Disable High High Deasserted Sync Read Low High Active 2 Async Read Low High Deasserted Write High Low Deasserted |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |