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Numonyx™ StrataFlash® Cellular Memory (M18)
Datasheet
April 2008
44
309823-10
Ceramic chip capacitors of 0.01 to 0.1 µF capacitors should be used between all VCC,
VCCQ, VPPsupply connections and system ground. These high-frequency, inherently
low-inductance capacitors should be placed as close as possible to the device package,
or on the opposite side of the printed circuit board close to the center of the device-
package footprint.
Larger (4.7 µF to 33.0 µF) electrolytic or tantulum bulk capacitors should also be
distributed as needed throughout the system to compensate for voltage sags caused by
circuit trace inductance.
Transient current magnitudes depend on the capacitive and inductive loading on the
device’s outputs. For best signal integrity and device performance, high-speed design
rules should be used when designing the printed-circuit board. Circuit-trace
impedances should match output-driver impedance with adequate ground-return
paths. This will help minimize signal reflections (overshoot/undershoot) and noise
caused by high-speed signal edge rates.
6.2
DC Current Specifications
The M18 device includes specifications for different lithographies, densities, and
frequencies. For additional information on combinations, see Table 4, “M18 Product
Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional
Description.
Table 13: DC Current Specifications (Sheet 1 of 3)
Sym
Parameter
Litho
(nm)
Density
(Mbit)
1.7 V – 2.0 V
Unit
Test Conditions
Notes
Typ
Max
ILI
Input Load Current
—
±1
µA
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS
1
ILO
Output Leakage Current
—
±1
µA
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS
ICCS
VCC Standby
90
256
512
35
50
95
120
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCCQ
RST# = VCCQ or GND
(for ICCS)
WP# = VIH
1,2
65
128
256
512
1,024
45
50
60
70
115
130
160
185
ICCAPS
APS
90
256
512
35
50
95
120
µA
VCC = VCC Max
VCCQ = VCCQ Max
CE# = VSSQ
RST# = VCCQ
All inputs are at rail to
rail (VCCQ or VSSQ).
—
65
128
256
512
1,024
45
50
60
70
115
130
160
185



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