JS48F4400P0P3C0 datasheet(43/139 Pages) NUMONYX

43 / 139 page

April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

6.0

Electrical Characteristics

6.1

Initialization

Proper device initialization and operation is dependent on the power-up/down

sequence, reset procedure, and adequate power-supply decoupling. The following

sections describe each of these areas.

6.1.1

Power-Up/Down Characteristics

To prevent conditions that could result in spurious program or erase operations, the

power-up/power-down sequence shown in Table 12 is recommended. Note that each

power supply must reach its minimum voltage range before applying/removing the

next supply voltage.

* Power supplies connected or sequenced together.

Device inputs must not be driven until all supply voltages reach their minimum range.

RST# should be low during power transitions.

Note:

If VCCQ is below VLKOQ, the device is reset.

6.1.2

Reset Characteristics

During power-up and power-down, RST#should be asserted to prevent spurious

program or erase operations. While RST#is low, device operations are disabled; all

inputs such as address and control are ignored; and all outputs such as data and WAIT

are placed in High-Z. Invalid bus conditions are effectively masked out.

Upon power-up, RST#can be deasserted after tVCCPH, allowing the device to exit from

reset. Upon exiting from reset, the device defaults to asynchronous Read Array mode,

and the Status Register defaults to 0080h. Array data is available after tPHQV, or a bus-

write cycle can begin after tPHWL.

If RST#is asserted during a program or erase operation, the operation will abort and

array contents at that location will be invalid.

For proper system initialization, connect RST#to the low-true reset signal that asserts

whenever the processor is reset. This will ensure the flash device is in the expected

read mode (i.e., Read Array) upon startup.

6.1.3

Power Supply Decoupling

High-speed flash memories require adequate power-supply decoupling to prevent

external transient noise from affecting device operations, and to prevent internally-

generated transient noise from affecting other devices in the system.

Table 12: Power-Up/Down Sequence

Power Supply

Voltage

Power-Up Sequence

Power-Down Sequence

VCC(min)

1st

1st*

Sequencing not

required*

3rd

2nd

2nd*

Sequencing not

required*

VCCQ(min)

2nd

2nd*

2nd

1st*

VPP(min)

3rd

2nd

1st

JS48F4400P0P3C0 bảng dữ liệu(PDF) 43 Page - Numonyx B.V

JS48F4400P0P3C0 bảng dữ liệu(HTML) 43 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL