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JS48F4400P0P3C0 bảng dữ liệu(PDF) 49 Page - Numonyx B.V |
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JS48F4400P0P3C0 bảng dữ liệu(HTML) 49 Page - Numonyx B.V |
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49 / 139 page ![]() April 2008 Datasheet 309823-10 49 Numonyx™ StrataFlash® Cellular Memory (M18) Notes: 1. See the following table for component values. 2. Test configuration component value for worst case speed conditions. 3. CL includes jig capacitance. 7.2 Read Specifications Read specifications for 108 MHz and 133 MHz M18 devices are included here. For additional information on lithography, density, and frequency combinations, see Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional Description. Devices which support frequencies up to 133 MHz must meet additional timing specifications for synchronous reads (for address latching with CLK) as listed in Table 20, “AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V” on page 51. Table 17: AC Input Requirements Symbol Parameter Frequency Min Max Unit Condition tRISE/FALL Inputs rise/fall time (Address, CLK, CE#, OE#, ADV#, WE#, WP#) @133MHz, 108MHz 0.3 1.2 ns VIL to VIH or VIH to VIL @66MHz 0 3 tASKW Address-Address skew 0 3 At VCCQ/2 Figure 19: Transient Equivalent Testing Load Circuit Table 18: Test Configuration Component Value for Worst Case Speed Conditions Test Configuration CL (pF) 1.7 V Standard Test 30 2.0 V Standard Test 30 Figure 20: Clock Input AC Waveform Device Under Test Out C L CLK [C] V IH V IL R203 R202 R201 CLKIN PUT.vsd V CC Q/2 |
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