JS48F4400P0P3C0 datasheet(135/139 Pages) NUMONYX

135 / 139 page

April 2008

Datasheet

309823-10

135

Numonyx™ StrataFlash® Cellular Memory (M18)

Notes:

Diagram shows WAIT as active low (RCR.10=0) and asserted with Data (RCR.8=0).

For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in timing diagram)

Without latching A[MAX:16] in the Sync Read Cycle, the previously latched A[MAX:16] applies.

A.3.4

Synchronous Write Cycles

For synchronous writes, only the address latching cycle(s) are synchronous.

Synchronous address latching is depicted in the timing diagrams for synchronous read

cycles:

• Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address

Cycles)” on page 134

• Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address

Cycles)” on page 134

• Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135

The actual write operation (rising WE# edge) is asynchronous and is independent of

CLK. Asynchronous writes are depicted in the timing diagrams for asynchronous write

cycles:

• Figure 63, “AADM Asynchronous Write Cycle (Latching A[MAX:0])” on page 132

• Figure 64, “AADM Asynchronous Write Cycle (Latching A[15:0] only)” on page 132

A.3.5

System Boot

Systems that use the AADM mode will boot from the bottom 128k Bytes of device

memory because A[MAX:16] are expected to be grounded in-system. The 128k Byte

boot region is sufficient to perform required boot activities before setting RCR[4] to

enable AADM mode.

Figure 67: AADM Sync Burst Read Cycle (Latching A[15:0] only)

A[15:0]

DQ[15:0]

R312

R307

R314

R303

R317

R313

R311

R302

R305

R304

R315

R306

R301

A/DQ[15:0]

CLK

ADV#

CE#

OE#

WE#

WAIT

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