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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS5802PWPR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TAS5802PWPR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 106 page  5.6 Timing Requirements MIN NOM MAX UNIT Serial Audio Port Timing - Target Mode fSCLK SCLK frequency 1.024 MHz tSCLK SCLK period 40 ns tSCLKL SCLK pulse width, low 16 ns tSCLKH SCLK pulse width, high 16 ns tSL SCLK rising to LRCLK/FS edge 8 ns tLS LRCK/FS Edge to SCLK rising edge 8 ns tSU Data setup time, before SCLK rising edge 8 ns tDH Data hold time, after SCLK rising edge 8 ns tDFS Data delay time from SCLK falling edge 15 ns I2C Bus Timing – Standard fSCL SCL clock frequency 100 kHz tBUF Bus free time between a STOP and START condition 4.7 µs tLOW Low period of the SCL clock 4.7 µs tHI High period of the SCL clock 4 µs tRS-SU Setup time for (repeated) START condition 4.7 µs tS-HD Hold time for (repeated) START condition 4 µs tD-SU Data setup time 250 ns tD-HD Data hold time 0 3450 ns tSCL-R Rise time of SCL signal 20 + 0.1CB 1000 ns tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1CB 1000 ns tSCL-F Fall time of SCL signal 20 + 0.1CB 1000 ns tSDA-R Rise time of SDA signal 20 + 0.1CB 1000 ns tSDA-F Fall time of SDA signal 20 + 0.1CB 1000 ns tP-SU Setup time for STOP condition 4 µs CB Capacitive load for each bus line 400 pf I2C Bus Timing – Fast fSCL SCL clock frequency 400 kHz tBUF Bus free time between a STOP and START condition 1.3 µs tLOW Low period of the SCL clock 1.3 µs tHI High period of the SCL clock 600 ns tRS-SU Setup time for (repeated)START condition 600 ns tRS-HD Hold time for (repeated)START condition 600 ns tD-SU Data setup time 100 ns tD-HD Data hold time 0 900 ns tSCL-R Rise time of SCL signal 20 + 0.1CB 300 ns tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1CB 300 ns tSCL-F Fall time of SCL signal 20 + 0.1CB 300 ns tSDA-R Rise time of SDA signal 20 + 0.1CB 300 ns tSDA-F Fall time of SDA signal 20 + 0.1CB 300 ns tP-SU Setup time for STOP condition 600 ns tSP Pulse width of spike suppressed 50 ns CB Capacitive load for each bus line 400 pf 5.7 Typical Characteristics TAS5802 SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025 www.ti.com 8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TAS5802 |
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