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TAS5802PWPR bảng dữ liệu(PDF) 54 Page - Texas Instruments |
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TAS5802PWPR bảng dữ liệu(HTML) 54 Page - Texas Instruments |
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54 / 106 page ![]() 7.1.14 CLKDET_STATUS Register (Offset = 39h) [Reset = 00h] CLKDET_STATUS is shown in Figure 7-14 and described in Table 7-16. Return to the Summary Table. Clock detection status Figure 7-14. CLKDET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED BCLK_OVERR ATE PLL_OVERRAT E PLL_LOCKED BCLK_MISSIN G BCLK_VALID FS_VALID R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 7-16. CLKDET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5 BCLK_OVERRATE R 0h This bit indicates whether the BCLK is overrate or underrate. 0: BCLK is underrate 1: BCLK is overrate 4 PLL_OVERRATE R 0h This bit indicates whether the PLL is overrate or not. 0: PLL is underrate 1: PLL is overrate 3 PLL_LOCKED R 0h This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled. 0: PLL is locked 1: PLL is not locked 2 BCLK_MISSING R 0h This bit indicates whether the BCLK is missing or not. 0: BCLK is normal 1: BCLK is missing 1 BCLK_VALID R 0h This bit indicates whether the BCLK is valid or not. The BCLK ratio must be stable and in the range of 32-512FS to be valid. 0: BCLK is valid 1: BCLK is not valid 0 FS_VALID R 0h In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid. In non auto detection mode(reg_fsmode!=0), FS error indicates that configured sampling frequency set by LRCLK(FS) is different with detected sampling frequency. Even if FS Error Detection Ignore is set, this flag will be also asserted. 0: Sampling rate is valid 1: Not valid TAS5802 SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025 www.ti.com 54 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TAS5802 |
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