TUSB2E2211005VBW datasheet(51/63 Pages) TI2

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10.2.2.1 eUSB PHY Settings Recommendation

Table 10-1 shows the recommended eUSB PHY register settings for different eUSB lengths.

Table 10-1. Recommended eUSB PHY Settings based on FR4 length

eUSB PHY Register

2.5 inches

5 inches

7.5 inches

10 inches

E_EQ_Px

E_HS_TX_AMPLITUDE_Px

E_HS_PRE_EMPHASIS_Px

10.2.3 Application Curve

Figure 10-2. Typical USB 2.0 High-Speed Eye Diagram

10.3 Power Supply Recommendations

10.3.1 Power-Up Reset

The RESETB pin is an active-low reset pin that can also be used as a power-down pin.

The TUSB2E221 does not have power supply sequence requirements between VDD3V3 and VDD1V8.

Make sure the maximum VDD3V3 and VDD1V8 ramp time to reach minimum supply voltages is 2ms.

An internal power-on reset circuit along with the external RESETB input pin allows for proper initialization when

RESETB is deasserted high prior to the power rails being valid. If RESETB deasserts high before the power

supplies are stable, the internal power-on reset circuit can hold off internal reset until the supplies are stable.

After the RESETB deassertion, followed by internally generated reset signal and 1ms delay, CROSS pin is

sampled and latched.

After the RESETB deassertion and after t_RH_READY, the TUSB2E221 is enabled and enters default state, ready

to accept eUSB2 packets. Each repeater is either in host repeater mode or device repeater mode depending on

the receipt of either host mode enable or peripheral mode enable.

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TUSB2E221

SNLS757D – JUNE 2024 – REVISED OCTOBER 2025

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TUSB2E2211005VBW bảng dữ liệu(PDF) 51 Page - Texas Instruments