TUSB2E2211005VBW datasheet(30/63 Pages) TI2

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4. The TUSB2E221 acknowledges the register offset cycle.

5. The host presents a repeated start condition (Sr).

6. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E221 7-bit

address and a one-value “W/R” bit to indicate a read cycle.

7. The TUSB2E221 acknowledges the 7-bit address cycle.

8. The TUSB2E221 transmit the contents of the memory registers MSB-first starting at the register offset.

9. The TUSB2E221 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host

after each byte transfer; the I2C host acknowledges reception of each data byte transfer.

10. If an ACK is received, the TUSB2E221 transmits the next byte of data as long as host provides the clock. If a

NAK is received, the TUSB2E221 stops providing data and waits for a stop condition (P).

11. The host terminates the read operation by generating a stop condition (P).

Figure 8-8. I2C Write Without Data

Use this procedure to set a starting sub-address for I2C reads (refer to Figure 8-8).

1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E221 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB2E221 acknowledges the address cycle.

3. The host presents the register offset within the TUSB2E221 to be written, consisting of one byte of data,

MSB-first.

4. The TUSB2E221 acknowledges the register offset cycle.

5. The host terminates the write operation by generating a stop condition (P).

Note

After initial power-up, if no register offset is included for the read procedure (refer to Figure 8-6),

then reads start at register offset 00h and continue byte by byte through the registers until the I2C

host terminates the read operation. During a read operation, the TUSB2E221 auto-increments the

I2C internal register address of the last byte transferred independent of whether or not an ACK was

received from the I2C host.

tBUF

tHDSTA

tLOW

tHDDAT

HIGH

tSUDAT

tSUSTA

tHDSTA

tSUSTO

SDA

SCL

30%

70%

30%

70%

Figure 8-9. I2C Timing Diagram

8.5.2 Register Access Protocol (RAP)

Each repeater in the TUSB2E221 supports the register access protocol (RAP) over eUSB2 to allow access to

the related registers. Only the registers associated with each repeater is accessible through RAP. Registers for

the other repeater or the chip top level are not accessible through RAP.

TUSB2E221

SNLS757D – JUNE 2024 – REVISED OCTOBER 2025

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