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D950-Core

HOLD State

This function allows the release of the buses for another device such as a DMA controller (see

Section 6.3.6).

Entering HOLD state: The HOLD signal is sampled at the beginning of every cycle. When

HOLD is recognized low, the processor immediately releases the I-bus and then releases the

X and Y buses after execution of the currently decoded instruction. Bus address, data and

control lines are then tri-stated.

Program execution is stopped and HOLDACK is asserted low during HOLD state.

Note:HOLD state can not be entered when the processor is in emulation mode.

Exit of HOLD state: The processor recovers bus mastership as soon as HOLD is sampled

high and next instruction is fetched.

HALT State

This function is used in emulation mode only. It is used to stop program execution by use of

the peripheral emulator unit (see Section 7.5).

4.3.8 Memory Moves with Wait States

DTACK input is used to stretch instruction cycles, in order to access slower memory and/or

peripherals. DTACK is sampled on the rising edge of CLKIN. If DTACK is high on the third

rising edge of the cycle, the cycle is extended by two CLKIN cycles (see Section 6.3.4).

Extension cycles are added by the clock generator until DTACK is recognized low.

Note:

DTACK generation can be controlled by the Bus Switch Interface peripheral (see Section 7.2).

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