D950-CORE datasheet(74/89 Pages) STMICROELECTRONICS

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D950-Core

For the following examples, ‘-’ means RESERVED (read: 0, write: don't care)

IMi:

Interrupt Mask

0: Interrupt i is not masked

1: Interrupt i is masked (def.)

ISi:

Sensitivity

0: ITRQi is active on a low level (def.)

1: ITRQi is active on a falling edge

IPR: Interrupt Priority Register

IPR contains the priority level of each ITRQi interrupt input.

Interrupt priority level is a 2-bit value, so can be 0,1,2 or 3 (0 lowest priority, 3 highest priority).

When two ITRQi of same priority level are requested during the same cycle, the first

acknowledged interrupt is the interrupt corresponding to the lowest numberical value.

After reset, IPR default value is 0.

IPi:

Interrupt Priority level (0, 1, 2 or 3) (def. 0)

ICR: Interrupt Control Register

ICR displays the current priority level and up to four stacked priority levels.

The current priority level is coded using 3 bits but only five different values are available:

Note:

The D950-Core interrupts (SWI, RESET) are priority level 4 (highest level).

An interrupt request is acknowledged when its priority level is strictly higher than the current

priority level. In this case, the current priority level becomes the interrupt priority level and the

previous current priority level is pushed onto the stack and displayed as SPL1.

IS7IM7

IS6IM6

IS5

IM5

IS4

IM4

IS3IM3

IS2IM2

IS1IM1

IS0

IM0

15 - 14

13 - 12

11 - 10

9 - 8

7 - 6

5 - 4

3 - 2

1 - 0

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

PRIORITY LEVEL

CODING

ACCEPTABLE IT LEVEL PRIORITY

- 1

111

0,1,2,3

000

1,2,3

001

2,3

010

011

Reserved

100 - 110

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