D950-CORE datasheet(75/89 Pages) STMICROELECTRONICS

75 / 89 page

75/89

D950-Core

The process is repeated over a range of four interrupt requests and the four previous current

priority levels are displayed as SPL1, SPL2, SPL3 and SPL4. If less than four interrupts are

pushed onto the stack, the unused Stack Priority Level words are reset to ‘000’.

At the end of the interrupt routine, the priority levels are popped from the stack.

If the SPLi values are directly written, the register content is not more significant but the

interrupt routine procedure is not affected. The only way to affect this is to reset the AS-DSP.

After reset, ICR default value is 0x000B.

SPL4:

3-bit 4th stacked priority level

SPL3:

3-bit 3rd stacked priority level

SPL2:

3-bit 2nd stacked priority level

SPL1:

3-bit 1st stacked priority level

ES:

Empty Stack flag

0: Stack is used

1: Stack is not used (def.)

CPL:

Current Priority level (-1, 0, 1, 2 or 3) (def. 011)

Note:After reset, no interrupt request from interrupt controller is acknowledged.

‘-’ means RESERVED (read: 0, write: don't care)

Figure 7.4

ICR and ISPR Operation

15 - 14 - 13

12 - 11 - 10

9 - 8 - 7

6 - 5 - 4

2 - 1 - 0

SPL4

SPL3

SPL2

SPL1

CPL

INTERRUPT LEVEL 2

PROGRAM

IT2

PROGRAM

IT3

IT2

IT3

INTERRUPT LEVEL 3

-1

SPL4 SPL3 SPL2 SPL1 ES CPL

-1

SPL4 SPL3 SPL2 SPL1 ES CPL

-1

ISP

ICR

ISPR

VR02020D

D950-CORE bảng dữ liệu(PDF) 75 Page - STMicroelectronics

D950-CORE bảng dữ liệu(HTML) 75 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

bảng dữ liệu tải về

Link URL