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ADC32RF44IRMPR bảng dữ liệu(PDF) 122 Page - Texas Instruments |
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ADC32RF44IRMPR bảng dữ liệu(HTML) 122 Page - Texas Instruments |
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122 / 135 page ![]() Matching Network 100- Differential 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 DB1P GND DB1M DB2M GPIO3 VCM AVDD19 GND GND DA0P DA1M AVDD ADC32RF44 GND Pad (Back Side) DVDD DA1P DA0M GPIO4 DVDD SYSREFM SYSREFP GND AVDD19 GND CLKINM CLKINP GND AVDD GPIO1 GPIO2 DB0M DB0P DVDD DB2P 17 18 36 SYNCBM SYNCBP 54 53 56 55 DA2P DA2M 35 10 nF GND 10 nF 10 k DVDD 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 100- Differential Low Jitter Clock Generator 10 nF AVDD 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F DVDD DVDD 0.1 F GND DVDD 10 nF GND DVDD 0.1 F GND 0.1 F AVDD 0.1 F DVDD 0.1 F GND AVDD19 AVDD 0.1 F AVDD19 AVDD AVDD19 AVDD19 0.1 F Driver 0.1 F Driver AVDD19 DVDD Matching Network Matching Network SPI Master FPGA AVDD DVDD 0.1 F Copyright © 2017, Texas Instruments Incorporated AVDD19 0.1 F 122 ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 www.ti.com Product Folder Links: ADC32RF44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 10.2 Typical Application The ADC32RF44 is designed for wideband receiver applications demanding high dynamic range over a large input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 239. Decoupling capacitors with low ESL are recommended to be placed as close as possible at the pins indicated in Figure 239. Additional capacitors can be placed on the remaining power pins. Figure 239. Typical Application Implementation Diagram |
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