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ADC32RF44IRMPR bảng dữ liệu(PDF) 59 Page - Texas Instruments

tên linh kiện ADC32RF44IRMPR
Giải thích chi tiết về linh kiện  ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter
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ADC32RF44IRMPR bảng dữ liệu(HTML) 59 Page - Texas Instruments

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tSDOUT
SCLK
SDOUT
59
ADC32RF44
www.ti.com
SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017
Product Folder Links: ADC32RF44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Table 27. SPI Input Description
SPI BIT
DESCRIPTION
OPTIONS
R/W bit
Read/write bit
0 = SPI write
1 = SPI read back
M bit
SPI bank access
0 = Analog SPI bank (master)
1 = All digital SPI banks (main digital, interleaving,
decimation filter, JESD digital, and so forth)
P bit
JESD page selection bit
0 = Page access
1 = Register access
CH bit
SPI access for a specific channel of the JESD SPI
bank
0 = Channel B
1 = Channel A
ADDR[11:0]
SPI address bits
—
DATA[7:0]
SPI data bits
—
Figure 114 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT
bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.
Figure 114. SDOUT Timing



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