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ADC32RF44IRMPR bảng dữ liệu(PDF) 52 Page - Texas Instruments |
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ADC32RF44IRMPR bảng dữ liệu(HTML) 52 Page - Texas Instruments |
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52 / 135 page ![]() 52 ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 www.ti.com Product Folder Links: ADC32RF44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Device Functional Modes (continued) (1) In full rate output, the two LSBs are truncated to a 12-bit output. 9.4.2.2 JESD204B Frame Assembly The JESD204B standard defines the following parameters: • F is the number of octets per frame clock period • L is the number of lanes per link • M is the number of converters for the device • S is the number of samples per frame 9.4.2.3 JESD204B Frame Assembly in Bypass Mode Table 14 lists the available JESD204B formats and valid ranges for the ADC32RF44. The ranges are limited by the SerDes line rate and the maximum ADC sample frequency. The sample alignment for the bypass modes on the different lanes is shown in Table 15. Table 14. JESD Mode Options: Bypass Mode DECIMATION SETTING (Complex) OUTPUT RESOLUTION (Bits) L M F S 12-BIT MODE PLL MODE JESD MODE 0 JESD MODE 1 JESD MODE 2 MAX fCLK (Gsps) RATIO [fSerDes / fCLK (Gbps / GSPS)] Bypass 12(1) 8 2 8 20 3 16X 3 0 0 2.6 4 14 8 2 2 4 0 20X 1 0 0 2.5 5 (1) Blue shading indicates channel A and yellow shading indicates channel B. Table 15. JESD Sample Lane Alignments: Bypass Mode(1) OUTPUT LANE LMFS = 8224 LMFS = 82820 DA0 A0[13:6] A0[5:0], 00 A0[11:4] A0[3:0], A1[11:8] A1[7:0] A2[11:4] A2[3:0], A3[11:8] A3[7:0] A4[11:4] A4[3:0], 0000 DA1 A1[13:6] A1[5:0], 00 A5[11:4] A5[3:0], A6[11:8] A6[7:0] A7[11:4] A7[3:0], A8[11:8] A8[7:0] A9[11:4] A9[3:0], 0000 DA2 A2[13:6] A2[5:0], 00 A10[11:4] A10[3:0], A11[11:8] A11[7:0] A12[11:4] A12[3:0], A13[11:8] A13[7:0] A14[11:4] A14[3:0], 0000 DA3 A3[13:6] A3[5:0], 00 A15[11:4] A15[3:0], A16[11:8] A16[7:0] A17[11:4] A17[3:0], A18[11:8] A18[7:0] A19[11:4] A19[3:0], 0000 DB0 B0[13:6] B0[5:0], 00 B0[11:4] B0[3:0], B1[11:8] B1[7:0] B2[11:4] B2[3:0], B3[11:8] B3[7:0] B4[11:4] B4[3:0], 0000 DB1 B1[13:6] B1[5:0], 00 B5[11:4] B5[3:0], B6[11:8] B6[7:0] B7[11:4] B7[3:0], B8[11:8] B8[7:0] B9[11:4] B9[3:0], 0000 DB2 B2[13:6] B2[5:0], 00 B10[11:4] B10[3:0], B11[11:8] B11[7:0] B12[11:4] B12[3:0], B13[11:8] B13[7:0] B14[11:4] B14[3:0], 0000 DB3 B3[13:6] B3[5:0], 00 B15[11:4] B15[3:0], B16[11:8] B16[7:0] B17[11:4] B17[3:0], B18[11:8] B18[7:0] B19[11:4] B19[3:0], 0000 |
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