ADC32RF44IRMPR datasheet(29/135 Pages) TI2

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CLKIN

SYSREF

st SYSREF pulse.

Only the input clock

divider is reset.

tDLL

(Must be Kept > 40 Ps)

nd SYSREF pulse. If

the MASK CLKDIV bit is

set, the clock divider

ignores this pulse and

any subsequent

SYSREF pulses.

rd SYSREF pulse.

The NCO phase and

LMFC counter are reset.

MASK CLKDIV SYSREF Register Bit

1 (The input clock divider ignores the SYSREF pulses.)

MASK NCO SYSREF Register Bit

(1)

1 (The NCO and LMFC counter of the JESD interface

ignore the SYSREF pulses.)

th SYSREF pulse (and

subsequent pulses).

Ignored by the input clock

divider, NCO, and the JESD

interface.

ADC32RF44

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SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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The SESREF use-cases can be classified broadly into two categories:

1. SYSREF is applied as aperiodic multi-shot pulses.

Figure 69 shows a case when only a counted number of pulses are applied as SYSREF to the ADC.

Alternatively, the SYSREF buffer can be powered down with the PDN SYSREF bit.

Figure 69. SYSREF Used as a Periodic, Finite Number of Pulses

After the first SYSREF pulse is applied, allow the DLL in the clock path to settle by waiting for the tDLL time (>

40 µs) before applying the second pulse. During this time, mask the SYSREF going to the input clock divider

by setting the MASK CLKDIV SYSREF bit so that the divider output phase remains stable. The NCO phase

and LMFC counter are reset on the third SYSREF pulse. After the third SYSREF pulse, the SYSREF going

to the NCO and JESD block can be disabled by setting the MASK NCO SYSREF bit to avoid any unwanted

resets.

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