ADC32RF44IRMPR datasheet(27/135 Pages) TI2

27 / 135 page

CLKINP

100

SYSREFP

SYSREF

Capture

Delay

CLKINM

SYSREFM

Clock Amplitude (vPP)

0.2

100

150

200

250

300

350

D061

fIN = 1 GHz

fIN = 2 GHz

ADC32RF44

www.ti.com

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

Product Folder Links: ADC32RF44

Submit Documentation Feedback

Feature Description (continued)

The analog-to-digital converter (ADC) aperture jitter is a function of the clock amplitude applied to the pins. The

equivalent aperture jitter for input frequencies at a 1-GHz and a 2-GHz input (fS = 2.6 GSPS) is shown in

Figure 66. Depending on the clock frequency, a matching circuit can be designed in order to maximize the clock

amplitude.

Figure 66. Equivalent Aperture Jitter vs Input Clock Amplitude

9.3.3 SYSREF Input

The SYSREF signal is a periodic signal that is sampled by the ADC32RF44 device clock and is used to align the

boundary of the local multiframe clock inside the data converter. SYSREF is also used to reset critical blocks

[such as the clock divider for the interleaved ADCs, numerically-controlled oscillators (NCOs), decimation filters

and so forth].

The SYSREF input requires external biasing. Furthermore, SYSREF must be established before the SPI

registers are programmed. A programmable delay on the SYSREF input, as shown in Figure 67, is available to

help with skew adjustment when the sampling clock and SYSREF are not provided from the same source.

Figure 67. SYSREF Internal Circuit Diagram

ADC32RF44IRMPR bảng dữ liệu(PDF) 27 Page - Texas Instruments