ADC32RF44IRMPR datasheet(58/135 Pages) TI2

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tSLOADS

R/W

SDIN

SCLK

SEN

RESET

A11 A10

tDH

tDSU

tSLOADH

tSCLK

ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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9.4.3 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the

device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active

(low), as shown in Figure 113. The interface can function with SCLK frequencies from 20 MHz down to low

speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 26.

The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits

to distinguish between read/write, page and register, and individual channel access, as described in Table 27.

Figure 113. SPI Timing Diagram

Table 26. SPI Timing Information

MIN

TYP

MAX

UNIT

fSCLK

SCLK frequency (equal to 1 / tSCLK)

MHz

tSLOADS

SEN to SCLK setup time

tSLOADH

SCLK to SEN hold time

tDSU

SDIN setup time

tDH

SDIN hold time

tSDOUT

Delay between SCLK falling edge to SDOUT

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