ADC32RF44IRMPR datasheet(43/135 Pages) TI2

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Peak over 8

Samples

Output

of ADC

Block:

Peak over N

Samples (S`)

fS / 8

fS / (8N)

BLKPKDET

N = [1..2

16]

>THHigh

>THLow

Hysteresis

and DWELL

>TLHigh

>TLLow

Hysteresis

and DWELL

BLKPKDETH

BLKPKDETL

BLKTHHH,

BLKTHHL,

BLKTHLH,

BLKTHLL

DWELL

ADC32RF44

www.ti.com

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

Product Folder Links: ADC32RF44

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9.3.7 Eye Diagrams

Figure 101 and Figure 102 show the serial output eye diagrams of the ADC32RF44 at 5.0 Gbps and 12 Gbps

against the JESD204B mask.

Figure 101. Data Eye at 5 Gbps

Figure 102. Data Eye at 12 Gbps

9.3.8 Alarm Outputs: Power Detectors for AGC Support

The GPIO pins can be configured as alarm outputs for channels A and B. The ADC32RF44 supports three

different power detectors (an absolute peak power detector, crossing detector, and RMS power detector) as well

as fast overrange from the ADC. The power detectors operate off the full-rate ADC output prior to the decimation

filters.

9.3.8.1 Absolute Peak Power Detector

In this detector mode, the peak is computed over eight samples of the ADC output. Next, the peak for a block of

N samples (N × S`) is computed over a programmable block length and then compared against a threshold to

either set or reset the peak detector output (Figure 103 and Figure 104). There are two sets of thresholds and

each set has two thresholds for hysteresis. The programmable DWELL-time counter is used for clearing the

block detector alarm output.

Figure 103. Peak Power Detector Implementation

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