ADC32RF44IRMPR datasheet(28/135 Pages) TI2

28 / 135 page

Input Clock

Divider

(Divide-by-4)

ASSERT SYSREF REG

(In Master Page)

SEL SYSREF REG

(In Master Page)

CLKIN

(CLKP-CLKM)

SYSREF

(SYSREFP-SYSREFM)

DLL

NCO,

JESD Interface

(LMFC Counter)

MASK CLKDIV SYSREF

(In JESD Digital Page)

MASK NCO SYSREF

(In JESD Digital Page)

PDN SYSREF

(In Master Page)

ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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Product Folder Links: ADC32RF44

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Feature Description (continued)

9.3.3.1 Using SYSREF

The ADC32RF44 uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of

the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or

through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change

in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 68.

Figure 68. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter

The ADC32RF44 samples the SYSREF signal on the input clock rising edge. Required setup and hold time are

listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted,

whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after

disregarding the first two assertions, as shown in Table 1.

Table 1. Asserting SYSREF

SYSREF ASSERTION INDEX

ACTION

INPUT CLOCK DIVIDER

NCO PHASE

LMFC COUNTER

Gets reset

Does not get reset

Gets reset

Does not get reset

Gets reset

4 and onwards

Gets reset

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